description the gm71c4800c/cl is the new generation dynamic ram organized 524,288 x 8 bit. gm71c4800c/cl has realized higher density, higher performance and various functions by utilizing advanced cmos process technology. the gm71c4800c/cl offers fast page mode as a high speed access mode. multiplexed address inputs permit the gm71c4800c/cl to be packaged in standard 400 mil 28pin plastic soj. the package size provides high system bit densities and is compatible with widely available automated testing and insertion equipment. system oriented features include single power supply of 5v+/-10% tolerance, direct interfacing capability with high performance logic families such as schottky ttl. features * 524,288 words x 8 bit organization * fast page mode capability * single power supply (5v+/-10%) * fast access time & cycle time gm71c(s)4800c/cl-70 t rac t cac t rc 70 20 130 45 * low power active : 715/660 mw(max) standby : 5.5mw (cmos level : max) 1.1mw (l-series) * ras only refresh, cas before ras refresh, hidden refresh capability * all inputs and outputs ttl compatible * 1024 refresh cycles/16 a * 1024 refresh cycles/128 a (l-series) * battery back up operation (l-series) * self-refresh operation (gm71c4800c/cl) (unit: ns) 1 gm71c4800c gm71cs4800cl 524,288words x 8 bit cmos dynamic ram (top view) pin configuration 28 soj lg semicon co.,ltd. t pc gm71c(s)4800c/cl-60 60 18 110 40 ras v ss i/o0 i/o1 i/o2 i/o3 1 2 3 4 5 7 8 9 10 11 nc 6 we 12 13 14 a0 a1 a2 a3 v cc v ss i/o7 i/o6 i/o5 i/o4 24 25 26 27 28 nc 18 19 20 21 22 23 oe 15 16 17 a8 a7 a6 a5 a4 v ss cas a9
gm71c4800c gm71cs4800cl 2 pin description pin function pin function a0-a9 a0-a9 i/o0-i/o7 ras we v cc v ss nc address inputs refresh address inputs data-in/out row address strobe read/write enable power (+5v) ground no connection ordering information access time package gm71c4800cj-70 70 ? 400 mil 28 pin plastic soj cas column address strobe oe output enable type no. gm71c4800cj-60 60ns 400 mil 28pin plastic soj GM71CS4800CLJ-70 gm71cs4800clj-60 70 ? 60ns
gm71c4800c gm71cs4800cl 3 truth table ras cas we oe l l h h l h h h h h h h l l i/o0-i/o7 high-z high-z d out high-z i/o8-i/o15 high-z high-z high-z d out operation standby refresh lower byte read upper byte read l l h l d out d out word read l l l h d in don't care lower byte write l h l h don't care d in upper byte write l l l h d in d in word write l l h h high-z high-z h to l l - - high-z high-z cbr refresh or self refresh h to l h - - high-z high-z h to l l - - high-z high-z absolute maximum ratings* symbol parameter rating unit t a t stg v in /v out v cc i out 0 ~ 70 -55 ~ 125 -1.0 ~ 7.0 -1.0 ~ 7.0 50 ambient temperature under bias storage temperature (plastic) voltage on any pin relative to v ss voltage on v cc relative to v ss short circuit output current c c v v ma p d 1.0 power dissipation w *note: operation at or above absolute maximum ratings can adversely affect device reliability. recommended dc operating conditions* (t a = 0 ~ 70c) symbol parameter unit v cc v ih v il supply voltage input high voltage input low voltage v v v max 5.5 6.5 0.8 typ 5.0 - - min 4.5 2.4 -1.0 *note: all voltage reffered to vss
gm71c4800c gm71cs4800cl dc electrical characteristics (v cc = 5v+/-10%, t a = 0 ~ 70c) symbol parameter note v oh v ol output level output "h" level voltage (i out = -2ma) unit v v max v cc 0.4 min 2.4 0 output level output "l" level voltage (i out = 2ma) i cc1 ma 120 - 70 ? 1, 2 i cc2 ma 2 - i cc3 ma 2 i cc4 ma fast page mode current average power supply current (t pc = t pc min) 1, 3 120 - 70 ? 120 - 70 ? i cc5 standby current (cmos) power supply standby current (ras, cas, we, oe>=v cc -0.2v, d out =high-z) ma 1 - i cc6 ma cas-before-ras refresh current (t rc = t rc min) 120 - 70 ? i cc7 ua battery back up current (standby with cbr refresh) (t rc =125 s , t ras <=1 s , we, oe=v ih , cas =v il , d out =high-z) 300 - 4, 5 ua 200 - 4,5 i cc8 ma standby current ras = v ih cas = v il d out = enable 5 - 1 i i(l) ua 10 -10 i o(l) ua 10 -10 input leakage current any input (0v<=v in <=6.5v) output leakage current (d out is disabled, 0v<=v out <=6.5v) i cc9 self-refresh mode current (ras, cas<=0.2v, d out = high-z) 200 - 6 1 - gm71cs4800cl gm71c4800c note: 1. i cc depends on output load condition when the device is selected. i cc (max) is specified at the output open condition. 2. address can be changed once or less while ras = v il . 3. address can be changed once or less while lcas and ucas = v ih . 4. v ih >=v cc -0.2v, 0<=v il <=0.2v, address can be changed once or less while ras=v il . 5. l-series. 6. self-refresh series. (gm71c(s)4800c/cl) 4 operating current average power supply operating current (ras, cas cycling: t rc = t rc min) standby current (ttl) power supply standby current (ras, cas = v ih , d out = high-z) ras-only refresh current average power supply current (t rc = t rc min) 4 ma ua 60 ? - 60 ? - 60 ? - 60 ? - 130 130 130 130
gm71c4800c gm71cs4800cl read, write, read-modify-write and refresh cycles (common parameters) symbol parameter note max unit min t rc random read or write cycle time 130 - ? t rp ras precharge time 50 - ? t ras ras pulse width 70 10,000 ? t cas cas pulse width 20 10,000 ? t asr row address set-up time 0 - ? t rah row address hold time 10 - ? t asc column address set-up time 0 - ? t cah column address hold time 15 - ? t rcd ras to cas delay time 20 50 ? 8 t rad ras to column address delay time 15 35 ? 9 t rsh ras hold time 20 - ? t csh cas hold time 70 - ? t crp cas to ras precharge time 5 - ? t t transitiontime (rise and fall) 3 50 ? 7 t ref refresh period - 16 a capacitance (v cc = 5v+/-10%, t a = 25c) symbol parameter note c i1 c i2 c i/o input capacitance (address) input capacitance (clocks) output capacitance (data-in/out) 1 1 1, 2 unit ? ? ? max 5 7 7 min - - - note: 1. capacitance measured with boonton meter or effective capacitance measuring method. 2. oe= v ih to disable d out . ac characteristics (v cc = 5v+/-10%, t a = 0 ~ 70c, notes 1, 14, 15, 17, 18) - 128 a refresh period (l-series) 5 t dzo oe delay time from d in 0 - ? t dzc cas setup time from d in 0 - ? 19 19 20 t oed oe to d in delay time 20 - ? gm71c(s)4800 c/cl-70 test conditions input rise and fall times : 5ns output timing reference level : 0.8v, 2.4v input level : v il = 0v , v ih = 3.0v output load : 2ttl gate + c l (100pf) input timing reference level : 0.8v, 2.4v (including scope and jig) t cp cas percharge time 10 - ? 24 min 40 - 60 0 - 10 - 0 - 20 15 - - 5 - - 16 - 0 - 0 - - max gm71c(s)4800 c/cl-60 10,000 50 128 110 10 15 15 15 60 15 3 30 45 25 25 22
gm71c4800c gm71cs4800cl read cycle symbol parameter note max unit min t rac access time from ras - 70 ? t cac access time from cas - 20 ? t aa access time from address - 35 ? t rcs read command setup time 0 - ? t rch read command hold time to cas 0 - ? t rrh read command hold time to ras 0 ? t ral column address to ras lead time 35 - ? 2, 3 3, 4, 13 3, 5, 13 write cycle symbol parameter note max unit min t wcs write command setup time 0 - ? t wch write command hold time 15 - ? t wp write command pulse width 10 - ? t rwl write command to ras lead time 20 - ? t cwl write command to cas lead time 20 - ? t ds data-in setup time 0 - ? t dh data-in hold time 15 - ? 11, 21 11, 21 10, 19 6 t oac access time from oe - 20 ? 3 19 16, 19 16 19 21 gm71c(s)4800 c/cl-70 gm71c(s)4800 c/cl-70 t oh output data hold time 5 - ? t oho output data hold time from oe 5 - ? t off output buffer turn-off time 20 ? t oez output buffer turn-off time from oe 20 ? t cdd ? 24 20 6 cas to d in delay time 6 t clz 0 - ? cas to output in low-z 0 0 - - max min - 60 - 15 - 30 - - 0 30 - - 15 - - 15 15 0 - 0 0 - - gm71c(s)4800 c/cl-60 0 min 0 - - 10 - - - 0 - - max gm71c(s)4800 c/cl-60 0 5 5 15 15 15 15 15 t cal 35 - ? column address to cas lead time 30 -
gm71c4800c gm71cs4800cl read- modify-write cycle symbol parameter note max unit min t rwc read-modify-write cycle time 180 - ? t rwd ras to we delay time 95 - ? t cwd cas to we delay time 45 - ? t awd column address to we delay time 60 - ? 10 10 10 t oeh oe hold time from we 20 - ? 7 refresh cycle symbol parameter note max unit min t csr cas setup time (cas-before-ras refresh cycle) 10 - ? t chr cas hold time (cas-before-ras refresh cycle) 10 - ? t rpc ras precharge to cas hold time 10 - ? fast page mode cycle symbol parameter note max unit min t pc fast page mode cycle time 45 - ? ? t rasc fast page mode ras pulse width - 40 ? t acp access time from cas precharge ? t rhcp ras hold time from cas precharge 40 - ? 12 3, 13, 20 t cpw fast page moderead-modify-write cycle cas precharge to we delay time 65 - ? fast page mode read-modify-write cycle time 95 - 19 20 19 gm71c(s)4800 c/cl-70 gm71c(s)4800 c/cl-70 gm71c(s)4800 c/cl- 7 0 we setup time( cbr refresh cycle ) 10 - ? 100,000 t pcm t wrp 10,20 min - - - - 15 - max gm71c(s)4800 c/cl-60 max min - 10 - - gm71c(s)4800 c/cl-60 - max min - 100,000 - - - - gm71c(s)4800 c/cl- 6 0 150 80 35 50 10 10 10 40 35 35 55 80 - -
gm71c4800c gm71cs4800cl 8 self-refresh mode symbol parameter note max unit min t rass ras pulse width (self-refresh) 100 - ns t rps ras precharge time (self-refresh) 130 - ? t chs cas hold time (self-refresh) -50 - ? ac measurements assume t t = 5 ? . assumes that t rcd <=t rcd (max) and t rad <=t rad (max). if t rcd or t rad is greater than the maximum recommended value shown in this table, t rac exceeds the value shown. measured with a load circuit equivalent to 2 ttl loads and 100 ? . assumes that t rcd >=t rcd (max) and t rad <=t rad (max). assumes that t rcd <=t rcd (max) and t rad >=t rad (max). t off (max) define the time at which the output achieves the open circuit condition and are not referenced to output voltage levels. v ih (min) and v il (max) are reference levels for measuring timing of input signals. also, transition times are measured between v ih and v il . operation with the t rcd (max) limit insures that t rac (max) can be met, t rcd (max) is specified as a reference point only; if t rcd is greater than the specified t rcd (max) limit, then access time is controlled exclusively by t cac . operation with the t rad (max) limit insures that t rac (max) can be met, t rad (max) is specified as a reference point only; if t rad is greater than the specified t rad (max) limit, then access time is controlled exclusively by t aa . t wcs , t rwd , t cwd , t awd and t cpw are not restrictive operating parameters. they are included in the data sheet as electrical characteristics only ; if t wcs >=t wcs (min), the cycle is an early write cycle and thedata out pin will remain open circuit (high impedance) throughout the entire cycle; if t rwd >=t rwd (min), t cwd >=t cwd (min), t awd >=t awd (min) and t cpw >=t cpw (min), the cycle is a read modify write and the data output will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, the condition of the data out (at access time) is indeterminate. these parameters are referred to cas leading edge in early write cycle and to we leading edge in a delayed write or a read modify write cycle. t rasc defines ras pulse width in fast page mode cycles. access time is determined by the longer of t aa or t cac or t acp . an initial pause of 100 s is required after power up followed by a minimum of eight initialization cycles (ras only refresh cycle or cas before ras refresh cycle). if the internal refresh counter is used, a minimum of eitht cas before ras refresh cycles is required. notes: 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 21 gm71c(s)4800 c/cl-70 max min 100 - - - gm71c(s)4800 c/cl-60 110 -50
gm71c4800c gm71cs4800cl 15. 19. in delayed write or read-modify-write cycles, oe must disable output buffer prior to applying data to the device. either t rch or t rrh must be satisfied for a read cycle. the supply voltage with all vcc pins must be on the same level. the supply voltage with all vcc pins must be on the same level. do not enable d out buffer when using delayed write timing. if you use distributed cbr refresh mode with 15.6 s interval in normal read/write cycle, cbr refresh should be executed within 15.6 s immediately affter exiting from and before entering into self refresh mode. if you use ras only refresh or cbr burst refresh mode in normal read/write cycle, 1024 cycles of distributed cbr refresh with 15.6us interval should be executed within 16ms immediately after exiting from and before entering into self refresh mode. repetitive self refresh mode without refreshing all memory is not allowed. once you exit from self refresh mode, all memory cells need to be refreshed before re-entering the self refresh mode again. 16. 17. 18. 20. 21. 9
gm71c4800c gm71cs4800cl package dimensions unit: inches (mm) soj 0.730(18.54) max 0.7197(18.28) min 0.395(10.03) min 0.435(11.05) min 0.445(11.31) max 0.148(3.76) max 0.128(3.25) min 0.032(0.81) max 0.026(0.66) min typ 0.050(1.27) 0.360(9.15) min 0.380(9.65) max 0.025(0.64) min 0.405(10.29) max 0.020(0.51) max 0.015(0.38) min
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